An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic ⁄
Pedro Echeverr, Marisa López‐Vallejo · 2006
In this work we present an FPGA implementation of a single-precision ∞oating-point arithmetic powering unit. Our powering unit is based on an indirect method that transforms x y into a chain of operations involving a logarithm, a multiplication, an exponential function and dedicated logic for the case of a negative base. This approach allows to use the full input range for the base and exponent without limiting the range of the exponent as in direct methods. A tailored hardware implementation is exploited to increase the accuracy of the unit reducing the relative errors of the operations while high performance is obtained taking advantage of the FPGA capabilities for parallel architectures. A careful design of the pipeline stages of the involved operators allows a clock cycle of 201.3 MHz on a Xilinx Virtex-4 FPGA.