CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS
R. Rodriguez-Montaiibs · 1991
Logic testing has some well known limitations for circuits with failures causing intermediate voltage levels or, even, correct logic outputs with parametric deuiations from the fault free specificattons. For these failures current testing might be considered as a complementary technique to logic testing. In this work, these physical defects widely encountered in ioday’s CMOS processes, are modelled taking into account the topology of the defective circuit and the parameters of the technology used. These models are used to simulate at electrical level (SPICE) the behaviour of a simple three inverter chain with a faulty inverter. The merits of current testing in front of voltage testing are studied for the classes of defects modelled.