A Low Complexity VLSI ArchitectureforReed
Solomon Decoder · 2007
Reed-Solomon (RS)codeshavebeenwidely usedin a variety ofcommunication systems toprotect digital data against errors or toreducethesignal tonoiseratio requirement intransmission process. Thispaper presents an area-efficient 8-errorcorrecting RS (255,239) decoder architecture using RiBMalgorithm, implemented ona0.25-,um CMOS technology witha supply voltage of2.75V. Thetotal numberofgates isabout12,600, whichillustrates aboutanorder ofmagnitude reduction compared toexisting RSdecoders. This improvement inhardwarecomplexity isduetousinga low complexity multiplier overGF(28) andconstant multipliers. Thedecoder hasadataprocessing rateof1.6Gbits/s ataclock frequency of200MHz.