Architectural Design to Characterize Malignant Breast Lesion
Chatterjee Subarna, K Ray Ajoy, Rezaul Karim, Arindam Biswas · International Journal of Computer Applications · 2011
cancer, the second-leading cause of cancer deaths in American women, is the disease women fear most all over the world. Efficient technique for medical diagnosis is defined to provide better chance of a proper treatment. In this paper, we present a new parallel processing architecture to perform medical detection that uses multiple ultra-sono-graphic features and a diagnostic algorithm for identifying breast nodule malignancy. The algorithm has been implemented in the first phase without breaking them into macro-blocks, and in the next phase after breaking the frames into the respective macro- blocks. MATLAB has been used for the simulation of the algorithm and the results obtained are presented in this paper. We have also done the simulation and FPGA based synthesis of the proposed architecture for the most commonly used target hardware to analyze the hardware cost. In this paper, we have simulated an efficient image processing technique which utilizes a parallel data memory. The parallel data memory provides a faster data access for processing the image data. The proposed parallel architecture ensures high- speed operation and full utilization of the processing resources. Main Results: We have captured ultrasound images, collected and considered those frames which are suspected by radiologists. For processing of images we have used median filter to reduce the speckle noise, unsharp masking for contrast enhancement , binary thresholding and edge detection for mass segmentation and measured mass perimeter; calculated mass centroid, mass perimeter radial samples, FFT of the radial samples at higher frequencies for detection. We simulate the algorithm without breaking the image into macro-blocks (MB), and after breaking the image into the respective MB. We also analyze the results for different USG images in both the two cases. A parallel architecture based implementation of this algorithm is proposed. The parallel architecture features scalable, minimum processing elements, minimum clock cycles, low pin count so that it can achieve high performance, flexibility and low power consumption. Lastly the hardware requirement is estimated for various well known target architectures.