Floating-Point Design with Vivado HLS
James Hrica · 2012
This application note describes how the Vivado™ High-Level Synthesis (HLS) tool transforms a C/C++ design specification into a Register Transfer Level (RTL) implementation for designs that require floating-point calculations. While the basics of performing HLS on floating-point designs are reasonably straightforward, there are some more subtle aspects that merit detailed explanation. This application note presents details on the basics and advanced topics relating to design performance, area, and verification of implementing floating-point logic in Xilinx FPGAs using the Vivado HLS tool.