A Prototype for a Fault Tolerant Parallel Digital Signal Processor 3
Bruce R. Musicusl, A. Aliphas, Alexander J. Wei · Application-Specific Systems, Architectures, and Processors · 1990
We are currently building a hardware prototype of a fault-tolerant parallel digital signal processor, using the single fault correction scheme of Musicus, Song[1,2,3]. Ten of the sixteen DSP-32C processors perform identical linear operations on ten different data streams (a complex FFT for a sonar beamforming application), three do arithmetic checksums on the input data and FFT's on these checksums, and one generates the syndromes and does fault detection and correction using a Generalized Likelihood Ratio Test (GLRT). A faulty output from one of the first 13 processors can be detected and corrected without having to recalculate that output. The prototype is not itself fault-tolerant, but is intended to benchmark applications and to quantify the actual overheads involved in executing the fault-tolerance algorithm.