Session 3 Overview Microprocessor Technologies
Sonia Leon, Fabio Campi · 2009
Despite Gordon Moore’s own admonition that exponential transistor density scaling cannot go on forever, high-performance processor designers have continued to increase levels of chip integration, with resulting improvements in system performance. Growing core counts and cache sizes lead to faster systems but also result in numerous challenges. For one, off-chip communication becomes more of a performance bottleneck. Second, chip reliability, which is a requirement in the commercial market, becomes harder to achieve in the face of soft errors and manufacturing defects. Finally, efficient communication across such large chips at multi-GHz frequencies is becoming challenging. So, as process technology improvements have slowed, circuit innovations in these areas are more crucial to enabling processor designs to maximize performance through the concurrent optimization of process, circuits, and architecture trade-offs. These innovations are evident in four papers, which show new processor designs, and system architectures, while the other four describe fundamental building blocks for next-generation digital systems, including secure cryptographic engines, clock/frequency switching, on-chip interconnect, and die-temperature monitoring. The first two papers describe Intel’s next-generation of multi-core processors implemented in a 9M 45nm high-κ process. Paper 3.1 [Intel] marks another microprocessor milestone and introduces a 2.3B transistor Xeon processor including eight dual-threaded cores, four power domains, and increased reliability from double-error correction and triple-error detection in its caches. Paper 3.2 [Intel] expands the discussion to cover the entire processor family, which supports from 2 to 24MB shared L3 cache and I/O links providing 6.4 GT/s. Particular emphasis is placed on power management techniques including an on-chip power microcontroller and power gate transistors allowing power dissipation from sub-10W to 130W in different mobile, desktop and server segments. Paper 3.3 [NEC] examines system trade-offs enabled by separating on-chip memory onto a second layer flip-chip bonded atop a base logic chip. This system-in-package uses high-bandwidth 10µm-pitch micro-solder interconnect to exploit the benefits of increased memory re-configurability for mobile applications. This solution enable high-throughput inter-chip communication in systems-in-package, relieving the area pressure induced by ever-enlarging on-chip memory sizes as well as enabling innovative mixed-technology solution where memory is built in different process flavors than the computing logic. Paper 3.4 [Intel] presents the dynamic frequency switching system for clocking an Itanium processor. It switches between a pair of core PLLs with a single-cycle penalty and briefly throttles the cores to mitigate di/dt noise during switching. This ability allows the processor to deterministically follow dynamic workload and environmental conditions without performance penalty and to more tightly optimize and manage power dissipation.