In-System Eye Scan of a PCI Express Link with Vivado IP Integrator and AXI4
Luis Bielich · 2014
This application note describes a flow for integrating in-system Eye Scan into an AXI4-based system with Vivado ® IP integrator. When an AXI4-based processor is planned to be used in a design, it is simple to include Eye Scan functionality to a design by memory mapping the DRP interface of the transceiver to the AXI4 system. A reference design is provided to show how this is implemented with IP integrator. The Eye Scan algorithm from Eye Scan with MicroBlaze MCS [Ref 1] is leveraged in this application note to implement the Eye Scan processing. Eye Scan with MicroBlaze MCS [Ref 1] is a great application note for standalone Eye Scan, whereas this application note focuses on integration into an AXI4-based system. The reference design implements the Eye Scan functionality on a PCI Express ® link on the following reference boards: AC701, KC705, VC709, ZC706, and KCU105. Starting in 2013.3, Xilinx IP containing transceivers output the DRP interface to the top level of the IP. The integrated block for PCI Express IP is one of the IP cores including this major ease-of-use enhancement. This option enables the AXI4 system to memory map the DRP space of the transceivers without having to dive deep into the PCIe ® IP RTL. This ultimately maintains a clean IP flow enabling all of the plug-and-play benefits of the Vivado Integrated Design Environment (IDE). The Eye Scan results provide important information for validating the design of each channel across voltage, temperature and process. Along with the ability to validate the design of a channel, Eye Scan also provides a very high level of debug information not previously available in FPGA families.