A Novel Low-Power High-Resolution ROM-less DDFS Architecture
M. NourEldin, Ahmed Yahya · 2013
A low-power high-resolution ROM-less Direct Digital frequency synthesizer architecture based on FPGA Design is proposed. This paper is equipped to generate a sinusoidal waveform with a new simple design method, which is endowed with high speed, low power and high spurious free dynamic range (SFDR) features. The proposed low power methodology is achieved by two methods: first, in a phase accumulator design by selecting a pipelined phase accumulator with 8-bit components that has lowest number of four input LUTs and number of occupied Slices. Second, in the circuit of TSC by proposing the circuit without an external power source. The output frequency of proposed design is 195.35 kHz using built in clock frequency of 50MHz. However, the maximum operating frequency is 190.93MHz. In addition, the design has frequency resolution of 0.012Hz, which is promising to get very high tuning frequency with SFDR of 42 dBc or 70 dBFS.