A System Level Design Methodology for Architecture Exploration of Data Processing Systems
Alena Simalatsar · 2009
Electronic embedded systems are widely used for different purposes in our daily life, like communication, automation, measurements, security, and health. By their nature, these systems are often distributed and composed of nodes and processing elements that must interact with the environment and users, and communicate among themselves. The design of such architectures should take into account constraints on cost and physical size, which requires extensive analysis and performance evaluation. However, the growing complexity of electronic systems design and time-to-market pressure should not affect the correctness of new electronic systems. Existing design tools based on Register Transfer Level (RTL) are too detailed for an effective exploration of system design alternatives, and are typically biased towards specific implementation styles. This work is going to present a framework for fast architecture exploration and performance analysis of Data Processing Systems based on system-level specification languages and rapid architecture profiling using both existing and newly developed tools. Several methodologies have been developed for architectural exploration and design optimization based on the stepwise refinement of the design specification. One example is the platform-based design (PBD) methodology, based on the construction of different layers, called platforms, which represent different levels of the design abstraction, where platforms at higher levels abstract the details of lower level platforms. Our contribution is a framework that supports the PBD paradigm. Within the PBD, we have focused on the design abstraction that corresponds to the deployment of an application on a computing platform that may include general-purpose processors, digital signal processors, programmable or reconfigurable components (e.g., FPGAs) and interconnection elements. Each of the analyzed computing platforms can be a singleor double-processor based. The core of our framework is a model of a flexible scheduler that represents both processor and communication resources within a structured approach to the system performance evaluation. This approach includes not only performance metrics such as execution time, but also allows us to estimate the interprocessor communication overhead and evaluate different scheduling policies for both computation and communication.