Design of Universal Shift Register Using Reversible Logic
Jatiya Kabi, Kazi Nazrul · 2012
Reversible sequential circuits are considered the significant memory block for their ultra-low power consumption. Universal shift register is an important memory element of the sequential circuit family. In this paper we proposed efficient design of reversible universal shift register that is optimized in terms of quantum cost, delay and garbage outputs. Appropriate theorems and lemmas are presented to clarify the proposed designs and establish its efficiency.