Spartan-3A FPGA Implementation
Mohammed H. Al Mijalli, Saudi Arabia · 2012
This paper presents Spartan-3A devices; including, XC5S50A (package: tq144, speed grade: -5), XC3S200A (package: ft256, speed grade: -5), XC3S400A (package: Fg400, speed grade: -5), XC3S700A (package: fg484, speed grade: -5) field programmable gate array (FPGA) design and implementation using Very High speed integrated circuit Hardware Description Language (VHDL) based Braun's multipliers. The resources utilization is obtained for 4×4, 6×6, 8×8 and 12×12 Braun's multipliers. The comparison between Spartan-3A devices show same numbers for four input LUTs, occupied slices, bonded IOBs, total equivalent gate count but their average connection and maximum pin delays are different. For average and maximum pin delays all devices show to some extent comparable behaviour.