Floating-Point PID Controller Design with Vivado HLS and System Generator for DSP
Daniele Bagni, Duncan Mackay · 2013
Introduction Floating-point algorithms are widely used in industries from analysis to control applications. Traditionally, such algorithms have been implemented on microprocessors. The primary reason for using microprocessors has been the ease with which floating-point algorithms can be captured, validated, and debugged in C/C++ code, therefore avoiding the complexity and skills required to implement them in hardware. However, implementing these algorithms on optimized and dedicated hardware provides lower cost, higher performance, and power benefits over a standard, or even optimized microprocessor. This application note presents a new design flow enabled by the Xilinx Vivado™ Design Suite, which allows floating-point algorithms to be quickly specified in C/C++ code, optimized for performance, and implemented on Xilinx FPGA devices. This flow delivers on the cost, performance, and power benefits that have so far eluded designers who rely on traditional microprocessors for implementing floating-point algorithms. Starting from the standard industrial application of a Proportional-Integral-Derivative (PID) control, as reported in Vivado HLS Eases Design of Floating-Point PID Controller (Ref 1), we will review and explain the following aspects of implementing floating-point algorithms in an FPGA: 1. Explain benefits and opportunities created by implementing floating-point designs in an FPGA device 2. Review an industry standard application, showing how the algorithm can be implemented in C/C++ code.