Design and Simulation of Mathematical Models Using Mixed HDL Platform
Shruti R. Tambakhe, Ajay P. Thakare · 2014
We proposed the concept of simulation of mathematical model on mixed HDL-Simulink using Xilinx system generator. Many applications that are DSP based or certain communication application require mathematical modelling for their easy understanding and analysis. Due to its complexity Pure HDL is unable to simulate. Also it terms to be costly and time consuming process. A methodology for implementing DSP based or communication applications on a field programmable gate arrays (FPGA) using Xilinx System Generator (XSG) for Matlab. The DPSK system and FFT are simulated using Matlab/ Simulink environment and System Generator, a tool from Xilinx used for FPGA design as well as implemented on Spartan 3E Starter Kit boards. The implementation of FFT algorithms that can compute fourier transform of varied signals in real time for frequency analysis of signals on FPGAs (Spartan3E). With large demand for high dynamic range for applications, floating point implementation is used as fixed point implementation becomes increasingly expensive. The DPSK model are first board behaves as a modulator and the second as a demodulator. The modulator and demodulator algorithms have been implemented on FPGA using the VHDL language on Xilinx ISE. This paper provides a new approach towards the design and modeling of based complex mathematical model using mixed HDL platform of simulink and Xilinx form of the design architecture. In this model used Xilinx ISE software.The Hardware Description Languages (1), (3) (HDLs) have been developed for several years in this field. The HDLs and automated tools based on them have given new abilities to designers, however now they seem to be not sufficient. Now we are looking for tools that deal with models and descriptions on higher levels of abstraction and we would like to describe the entire system as a one piece i.e. without its initial, manual decomposition into the hardware and software. The terms of system level design, co-design and co-simulation have been well known for several years. The complexity of the systems has a strong impact on the models that are expected to reflect the functionality and timings of the real devices. The programming of the FPGA is done using a logic circuit diagram or a source code using a Hardware Description Language (HDL) to specify how the chip should work. FPGA or Field Programmable Gate Arrays can be programmed or configured by the user or designer after manufacturing and during implementation. Hence they are otherwise known as On-Site programmable. Unlike a Programmable Array Logic (PAL) or other programmable device, their structure is similar to that of a gate-array or an ASIC. The programmable logic blocks are called configurable logic blocks and reconfigurable interconnects are called switch boxes. Matlab is a high-level technical computing language and interactive environment for algorithm development, data visualization, data analysis, and numeric computation. In addition to the intellectual property functions provided in Matlab, the software packet is uniquely adept with vector and array based waveform data at the core of algorithms, which is suitable for applications such as image and video processing. Matlab-Simulink is an environment for multidomain simulation and Model-Based Design for dynamic and embedded systems. Matlab-Simulink is used in this application as the high level development tool in the design process. Xilinx System Generator, is a system-level modeling tool from Xilinx that facilitates FPGA hardware design. System Generator the use of simulates automatically launching an HDL simulator, generating additional HDL as needed (analogous to an HDL testbench), compiling HDL, scheduling simulation events, and handling the exchange of data between the Simulink and the HDL simulator. This is called HDL co-simulation. System Generator provides a generic interface that uses JTAG and a Xilinx programming cable (e.g., Parallel Cable IV or Platform Cable USB) to communicate with FPGA hardware. The model with the JTAG-based hardware co-simulation block implemented on Spartan 3E platform. In this paper two application are used one is FFT and another is DPSK system. In FFT is increased demand and advancements in product design in the field of communication, multimedia, security and safety equipment and other industrial and scientific products have created the need for high volume, low cost, multifunction, DSP based frequency analyzers that can use Fast Fourier Transform ( FFTs )for their signal processing or data manipulation. The paper deals with implementation of FFT algorithms that can compute fourier transform of varied signals in real time for frequency