Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System
Yuki Tanaka, Abderazek Ben Abdallah · 2015
High-performance 3D Network-on-Chips (3DNoCs) have become viable solutions for future many core systems. Through-Silicon-Via (TSV) is a prominent element of 3D-NoC design to support good performance and low power consumption. 3D-OASIS Network-on-Chips (3D-ONoC) was previously proposed in our laboratory. In this thesis, we integrate TSV connections in order to obtain a reliable 3DONoC router. We found out from the performance evaluation that the proposed router correctly delivers messages via the integrated TSV connections without observing any timing violations. We also noticed that the area of the proposed router is 51939μm, the power is 403μW, and the speed is 490.1MHz.