I/O and Memory Interfacing Features and Benefits in 7 Series Architecture
Matt Klein · 2011
The input and output (I/O) functionality in any FPGA needs to be designed to address a wide array of applications of varied performance and function. The I/O in the 7 series FPGAs and Zynq™ Embedded Processing Platforms (EPPs) from Xilinx have been optimized for a diverse set of requirements at both the physical and logical level, including high-speed memory, networking, video flat panel and sensor interfaces, high-speed ADC/DACs connectivity as well as legacy interfaces. Additionally, new hard blocks have been added specifically to benefit memory interfacing for high-speed DDR3 devices. This white paper describes how the new I/O structures in the 7 series architecture support the range of performance and functionality challenges needed to address the broad range of application needs.