MULTIPROCESSING HW/SW Recent Experience on an ESL Framework for Rapid Design Exploration using Hardware-Software Codesign for ARM-based FPGAs
Laurent Moss, Hubert Guérard, Gary Dare, Guy Bois · 2012
This paper presents an Electronic System Level (ESL) framework for the system specification, hardware/software (HW/SW) co-design and rapid design space exploration of electronic systems subject to Quality of Results (QoR) constraints such as performance, area and power. This framework is based on recent standards such as SystemC TLM-2.0 and IEEE 1685 (IP-XACT), and is enabled by the SpaceStudio TM tool suite, which incorporates novel research in virtual platform modeling, performance profiling and HW/SW co-design. The framework is demonstrated on a Motion-JPEG (M-JPEG) video decoder. We rapidly specified and evaluated 26 architectures and 14 power/performance trade-offs for the M-JPEG targeting the Xilinx Zynq platform, which combines an FPGA fabric and an ARM Cortex-A9 dual-core processor. These architectures used up to 2 of the ARM’s cores as well as 0 to 2 MicroBlaze soft-core processors, running with either bare-metal embedded software or the µCOS/II RealTime Operating System (RTOS), and differing in their HW/SW partitioning of application tasks. We show how the best architecture selection depends on the performance, area and power constraints.