Design Of A Parallel Pipelined FFT Architecture With Reduced Number Of Delays
Kiranraj A. Tank, Pradnya Pravin Zode · 2014
This paper presents a novel approach to design a four and eight parallel pipelined fast Fourier transform (FFT) architecture based on canonic signed digit multiplier. This approach is based on use of decimation in time algorithm which reduces the number of delay elements up to some extent compared to decimation in frequency based design. The number of delay elements required for an N point FFT architecture is N-4 which is comparable to that of delay feedback schemes. The number of complex adders required is approximately 50% less than the other feedback designs. The proposed architecture can be extended to any radix 2n based FFT algorithm. This proposed architecture is based on feed forward designs and can be pipelined up to more stages to increase the throughput.