A Low-Power VLSI architecture forIntra and Inter
George I. Stamoulis · 2006
TheH.264videocodingstandard canachieve considerably higher coding efficiency thanprevious standards. Thekeystothishighcodeefficiency aremainlythetwo prediction modes(Intra & Inter) provided bythestandard. Unfortunately thesecomeata costinconsiderable increased complexity attheencoder. Therefore itisofhighimportance to design architectures thatminimize thecostoftheprediction modes.Onecomputational element thatismetinboth, Inter andIntraPrediction modes,isthatoftheSumofAbsolute Differences (SAD). Inthis paperwepresent anewalgorithm thatcanreplace SADinthetwomainPrediction Modes,and whichcanprovide amoreefficient hardware implementation.