in TRON-Specification Chips From super-scalar architecture to low power consumption LSI
Shousuke Mori, Hideya Kishigarni, Ikuya Kawasaki, Yuichi Saitoh · 1993
The objective of this panel session is to survey directions that TRON-specification VLSI microprocessors will follow in the near and far terms. The panelists will offer their personal insights arid views with respect to the technologies about their own developped chip. Some of the issues to be addressed by the panel include the wggeslions in futuie architectures of TRONSpecification chips. The audience at the session is invited to challenge the panel's views aild propose alternative opinions or scenarios for these chips. It is hoped that some fertile understandings will be clarified which areas in future TRON-specification VLSI microprocessors may proceed.