CipherStream Protocol—How CoolRunner-II CPLDs Protect FPGA IP
J.W. Jenkins · 2003
It doesn’t usually take very long to create an FPGA design. Recently, however, Xilinx competitor ran an ad declaring that while an FPGA can take up to year to design, it can be cloned in only second. Are FPGA designs really that insecure? While the ad seems absurdly hyperbolic, it is true that the bitstreams of some volatile FPGAs can be cloned. While it’s unlikely that cloning could happen in a second, fears about the insecurity of design efforts are valid ones. To alleviate these anxieties, this white paper will show you how to substantially secure the bitstream and the overall design of FPGAs using Xilinx CoolRunner™-II CPLDs. It will not particularly address Virtex™-II and its successors because they already employ Triple DES bitstream encryption, which is considered by many to be sufficiently strong encryption to deter IP theft. It will rather focus on volatile FPGAs in general, including both Xilinx FPGAs and competitors’ FPGAs within its scope.