A Multiplier Based Parallel FIR filter
Swati Sorte · 2015
We aim to develop FIR (Finite Impulse Response) filter using new multiplier that works on dual port memory. The multiplier stores all possible pre- computed product values corresponding to all the possible input multiplicand values. When compared to the distributed architecture processor, this configuration has a reduced memory size and a less number of logic gates. The applications based on digital communication, speech processing make use of this processor. This processor has many other modules incorporated inside it such as 3:8 line address decoder, control circuit, 4bit to 3 bit address encoder, memory, barrel shift register, etc. This processor is designed and implemented using Hardware Description Language (HDL) where as to test and verify its functionality, the simulation is done using Xilinx.