Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits
Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith · 2005
The semiconductor era has been thriving since the past four decades but as we continually attain smaller chip sizes comprising of millions of transistors, the problems grow at an unmitigated speed too. Testing such huge circuits poses a huge problem unless tackled prudently. The best case scenario given the current circumstances would be to create a favorable test environment on-chip by implementing Design for Test (DFT) techniques. Asynchronous digital design methodologies are currently gaining popularity since they enjoy the benefits of reduced area, power and low EMI. In spite of several advantages, due to the absence of the global clock and the presence of more state holding gates, testing these circuits presents a challenge to the designer. A DFT implementation for one such asynchronous class known as Null Conventional Logic (NCL) circuits has been proposed in this paper. The methodology discussed, exploits the technique of test points’ insertion in order to improve the controllability of difficult feedback paths. Enhanced observability of long paths in the circuits is achieved by introducing of balanced tree structures or scan latches. This approach has been automated and works with industry standard tool suites, such as Mentor Graphics and Synopsis. The implemented tool transforms gate level NCL descriptions to those understood by the ATPG library provided with the DFT CAD tools. A test coverage increase of around 75% has been achieved with a less than 5% increase in terms of cost and area.