Reconfigured Low Power FPGA Architecture
M. Poornima · 2013
Field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads is presented in this paper. A low power A synchronous FPGA with LEDR encoding and 4-Phase dual Rail Encoding is designed in this paper. The power gating technique implemented in the proposed archit ecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous archi tectures. Moreover, detecting the data arrival in advance pre vents the delay increase for waking-up and the powe r consumption of unnecessary power switching. 4-Phase Dual Rail encoding is to achieve small area and LE DR encoding is to get high throughput and low power. L EDR encoding is done at input and 4-phase dual rail encoding is done at the output, which reduces power. Power g ating is done to each Logic Block, which shuts down power to the block which is ideal. Power reduction is achiev ed by selectively setting the functional units into a low leakage mode when they are inactive. The design is synthesi zed by using Xilinx and programmed using VHDL language and implemented using Xilinx tool. Since the power gating technique has small overheads, the granulari ty size of a power-gated domain is as fine as a single two-input and one-output lookup table.