Performance of Cyclic Redundancy Codes for Embedded Networks
Tridib Chakravarty, Phil Koopman · 2001
The Cyclic Redundancy Code (CRC) in a network message forms a primary defense against system failures. Because embedded systems often operate in noisy environments, it is vital that CRC polynomials be selected to be optimal with respect to detecting errors in expected traffic workloads. Unfortunately, most standard CRCs do not perform well for the short messages that are commonly sent in embedded system applications, and in general were apparently not designed with short messages in mind. This paper describes a methodology to determine an optimal CRC polynomial for applications using short messages. Additionally, standard 16-bit CRC polynomials are shown to be grossly suboptimal in error detection performance for short messages. Our methodology has identified an optimal 12-bit CRC that yields better error detection than the widely used CCITT 16-bit CRC for embedded network workloads having typical message lengths of 64 bits. Adoption of optimal CRCs would provide improved cost/detection performance tradeoffs for new dependable embedded system designs. 1.