Execute-in-Place (XIP) with AXI Quad SPI Using Vivado IP Integrator
Sanjay Kulkarni, Prasad Gutti · 2013
Summary This application note describes the eXecute-in-place (XIP) feature introduced in the AXI Quad SPI v3.0 IP core, released in the Vivado® Design Suite v2013.2. It provides information about the required connections to configure the FPGA from an SPI serial flash device, as well as the configuration flow for the SPI mode. It is designed for use with the Kintex®-7 (KC705) board with Numonyx SPI flash memory, but modifications in the software example file can be implemented for use on any Xilinx board. Many factors are involved in selecting the code execution method for a given embedded system, including materials cost, processor features, operating system capability and more. Most of the embedded application designs do not need a memory management unit, as the primary requirements might not be performance-oriented. XIP is a method of executing programs directly from long-term storage rather than copying it into block RAM. It is an extension of using shared memory to reduce the total amount of memory required. There are several criteria for using this mechanism. From the processor point of view, the storage should mimic regular memory that is operated at a faster rate. The program should be independent of location, and should not modify the image stored in the memory. If measured across all available memory sources, flash memory is preferred over Double Data Rate (DDR) or SRAM memories in embedded systems. Low power and a smaller pin interface count are additional benefits of flash memory. The aforementioned criteria are suited for parallel/serial flash memory. For 'boot from flash' operation, SPI-based flash memory is preferred due to advances in SPI flash technology, improved density, improved operating speed, and other vendor-based support. The executable code residing in the SPI flash is loaded into DDR through an XIP configured Quad SPI IP core to demonstrate the store and load feature of the XIP mode implemented. Along with this, two modes of XIP (Dual and Quad) are demonstrated to show the improvement in the data transfer in Quad mode.