FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics
Ravi Teja, A. Madhusudhan · 2013
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier using vedic mathematics .The purpose of using vedic mathematics is due to increase in the number of partial products in normal multiplication process ,with using vedic mathematics partial products can be reduced so that the area and power constraints of the floating point multiplier can be reduced efficiently. Keywords-floatingpoint; multiplication, FPGA, Nikhilamsutra, Radix selection unit, Vedic mathematics.