FAIR TIMING MASTER
M. Kreider, T. Fleck · 2010
In the scope of building the new FAIR facility, GSI will implement a new timing distribution system based on WhiteRabbit. The FAIR system will resemble a tree topology, with a single master unit on top, followed by several layers of WR switches, down to about two thousand timing receivers throughout the facility. The Timing Master will be a mixed FPGA/CPU solution, which translates physical requirements into timing events and feeds them into the WR network. Macros in the FPGA resemble a 32x multicore with a strongly reduced instruction-set, each event processor responsible for a specific part of the facility. These processors interact in real time, reacting to interlocks and conditions and ensuring determinism by parallel processing. A powerful CPU prepares the timing event sequences and provides an interface to the control system. These tables are loaded into the RAMs of each participating processor, controlling their behaviour and event output. GSI is currently working on the WR timing system in close collaboration with CERN, making this system the future of GSI/FAIR. This contribution covers technical details on the expected timing scenario, macro internals and discussion on possible future development.