Opt irnizat ion of Channel Segment at ion for Channelled Architecture FPGAs
Kaushik Roy, Mahesh M. Mehendale · 1992
This paper considers optimization of routing track segmentation for Channelled Architecture FPGAs. An algorithm has been developed which generates channel segmentation (with fixed length tracks) which approximates a given segment length distribution. Different channel architectures are evaluated using a segmented channel router which uses a bounded search algorithm for optimum channel routing.