A Constant Word-length Bit-Parallel Coordinate Rotation Digital Computer based Multiplier for Fixed-Point Digital Signal Processing Operations
Burhan Khurshid, Roohie Naaz Mir · 2015
Fixed-point multiplication is frequently used in many DSP algorithms. This paper considers the design of a constant wordlength bit-parallel fixed-point multiplier based on CORDIC algorithm. Traditional bit-parallel multipliers are designed using ripple-carry or carry-save logic. A comparative analysis of our implementation results against three widely used constant word-length bit-parallel fixed-point multipliers viz. ripple carry array multiplier, carry-save array multiplier and Bough-Wooley multiplier is presented in this paper. The comparison is made with respect to resource utilization, timing and power dissipation. The implementation is carried out for varying input word-lengths ranging from 4 to 32-bit parallel operands. Further, the implementation targets three different FPGA families viz. Spartan-6, Virtex-4, and Virtex-5. Our implementation achieves a reduction in resource usage by at least 30 %; increase in speed by at least 5 % and reduction in dynamic power dissipation by at least 20 %.