Fault Detection Technique For S-Box In AES Algorithm
M. P. Gomathi, M. Tamilselvi, N. JAYAPAL · 2014
Security of the info transmission is one among the prime factors in communication networks.So, authentication, nonrepudiation, information integrity associated confidentiality are the necessary elements of an info security. The principle of AES encryption algorithm and the detailed description of the FPGA design and implementation are proposed. The limitation of the current AES implementation methods is that the throughput is small. In allusion to this problem, this project applies assembly-line technology in the designation and gains the best optimized area and speed. The novel CFA AES S-boxes of the field is derived. The best construction is chosen when a sequence of recursive and subject optimization processes. What is more, for every composite field constructions, there exist eight attainable isomorphic mappings. Therefore, when the exploitation of a brand new common sub expression elimination algorithmic rule, the isomorphic mapping that leads to the minimum area is chosen. It implements AES encryption algorithm in hardware description language. A data corruption may be occurring due to SEU and to avoid this Hamming error correction code is used. The experiment result shows that high throughput is obtained.