High Speed Low Power Operations for FFT Using Reversible Vedic Multipliers
B. Sreelatha · 2014
Vedic mathematics can be aptly employed here to perform multiplication. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find application in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications. The Fast Fourier Transform (FFT) has become almost ubiquitous and most important in high speed signal processing. Another important area which any DSP engineer has to concentrate is the power dissipation, the first one being speed. There is always a tradeoff between the power dissipation and speed operation. The reversible computation is one such field that assures zero power dissipation. The goal of this paper is to develop a methodology to synthesize binary combinational reversible logic circuits in regular and non-regular structures, in binary logic, for multi-output functions, and minimizing a complex cost function.