TECHNOLOGY An Efficient Way of Decreasing the Latency of Flip Flops with Floating Point Multiplier
G Lalitha Rani · 2013
In this paper we proposed efficient implementatio n of floating point multiplier which is technology independent pipelined design. This also handles the case of overflow and underflow cases. This verifie d that they can decrease the flipflop latency over Xilinx flipf lop core.