An Area and Power Efficient Square Root Carry Select Adder Design by 3T-XOR Gate and Common Boolean Logic
E. Premkumar, G. Ashrafkhan · 2015
The Fastest adder among regular adder structure is known as Carry select adder (CSLA). This involves efficient CSLA interns of area, power and delay of the system. In this modified square root CSLA involves 3T-XOR gate design and Common Boolean logic (CBL) simplification. The 3 Transistor XOR gate reduces the number of transistors in the XOR gate of the adder circuit and after the logical simplification we need only one Inverter and one OR gate for summation and carry operation. Through the multiplexer, we can select the corresponding output accordance with logic states of the carry in signal. Based on this modification SQRT CSLA architecture have been developed and compared with the regular, Binary to Excess-1 (BEC) modified, CBL modified SQRT CSLA architectures. The proposed architecture achieves the advantages in terms of delay, area and power.