On analog decoders and digitally corrected converters
Frey, Matthias U. · Repository for Publications and Research Data (ETH Zurich) · 2006
In recent years, the demand for efficient and reliable communication networks has greatly increased. To satisfy this need, powerful error correcting codes were introduced. The (iterative) algorithms used for decoding such modern codes are computationally very demanding and need great computing power to deliver real-time results. Mobile users, however, ask for low-power electronics; the combination of both demands led to an increased interest in analog communication circuits, e.g., in analog decoders for error correcting codes. The first part of this thesis discusses various implementations of analog decoders. An analog decoder can be understood as a coderepresenting (factor) graph mapped on analog silicon, whereas the decoding algorithm (e.g., the sum-product algorithm) corresponds to the settling behavior of the analog circuit. The performance gain of analog decoders compared to digital implementations in terms of speed or power-consumption is believed to be at least a factor of 100. The following implementations of such analog decoders are discussed: Hamming decoders built out of two generations of discrete softgates, an integrated Hamming decoder and an integrated Reed-Muller decoder are presented. An extensive collection of measured error-rate curves of all decoders under various operating conditions prove their full functionality and demonstrate their behavior under transistor mismatch. Furthermore, a novel circuit to compute the soft symbols for a PAM or QAM signal is presented. This simple transistor network blends in nicely with analog decoders—its outputs are currents proportional to the symbol-likelihoods. vii