A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications
Chien‐Chang Lin, Jiawei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn‐Shyan Wang · IEEE Journal of Solid-State Circuits · 2007
In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm2silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory