A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
Blaine Stackhouse, Sal Bhimji, Chris Bostak, D. K. Bradley, B.S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, P.E. Gronowski, Dan Krueger, Charles R. Morganti, Steve Troyer · IEEE Journal of Solid-State Circuits · 2009
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.