A Neuron- and a Synapse Chip for Artificial Neural Networks
John A. Lansner, Torsten Lehmann · 1992
A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 μm CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 μs and the weight matrix has a 10 bit resolution.