Parallel paradigms and run-time management techniques for many-core architectures
Cristina Silvano, William Fornaciari, Stefano Crespi Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, Ch. Ykman-Couvreur, Alexandros Bartzas · 2012
The trend in computing architectures is currently replacing complex superscalar architectures with meshes of small homogeneous processing units connected by an on-chip network. This trend is mostly driven by inherent silicon technology frontiers, which are getting as closer as the process densities levels increase. The number of cores to be integrated in a single chip is rapidly increasing in the coming years, moving from multi-core to many-core architectures. This trend requires a global rethinking of software and hardware design approaches. Multi-core architectures are nowadays prevalent in general purpose computing and in high performance computing and more scalable multi-core architectures are and will be widely adopted for high-end graphics and media processing, e.g. IBM Cell BE, NVIDIA Fermi, SUN Niagara and Tilera TILE64.