A VLSI Processor for Fast Track Finding Based on Content Addressable Memories
A. Annovi, Antonio Bardi, M. Bitossi, S. Chiozzi, Carlo Damiani, M. Dell’Orso, P. Giannetti, P. Giovacchini, Giovanni Marchiori, Iván Pedron, M. Piendibene, L. Sartori, Sebastiano Fabio Schifano, Franco Spinella, S. Torre, R. Tripiccione · IEEE Transactions on Nuclear Science · 2006
The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology