A data-reuse architecture for gray-scale morphologic operations
Ming‐Hwa Sheu, Jie Wang, J.-S. Chen, An-Nan Suen, Yuan Long Jeang, J.-Y. Lee · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1992
Presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image, 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6) adaptability for N*N morphologic operations.>