FPGA Low Power Technology Mapping for Reuse Module Design under the Time Constraint
Jae‐Jin Kim, Hyeon-Mi Yang, Keun-Ho Ryu, Hi-Seok Kim · 2008
In this paper, FPGA low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis does not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using FPGA technology mapping algorithm for selection reuse module by scheduling.