Minimum drift architectures for 3-layer scalable DTV decoding
Anthony Vetro, Huifang Sun, P. DaGraca, T.C. Poon · IEEE Transactions on Consumer Electronics · 1998
This paper describes new techniques for implementing a low-cost video decoder that can decode an HDTV bitstream and display the signal at lower resolutions. Two key algorithms are discussed: downconversion and low-resolution motion compensation. In the proposed scheme, incoming blocks are subject to a down-conversion process within the decoding loop, hence motion compensation is performed from the downconverted images. The filters used for down-conversion are based on the concept of frequency synthesis, and the filters used to perform the low-resolution motion compensation are determined by an optimal least squares solution. Using these algorithms, three different architectures that provide equal quality with varying system level complexity are presented; the first is directly derived from the initial model of the low-resolution decoder, another attempts to reduce the amount of computation for the IDCT, while another addresses the concerns regarding the amount of interface with an existing decoder structure. All of the above systems are hierarchical with regard to the logic used for filtering and scalable in the amount of memory which is required to reconstruct each output layer. Our simulation results demonstrate that high quality video can be provided at lower-resolutions with significant memory savings.