An efficient FPGA implementation of a wavelet coder/decoder
N.A. Elghamery, S. E. D. Habib · 2002
This paper presents an efficient VLSI architecture for the one-dimensional discrete wavelet transform (DWT). The VLSI architecture is described using VHDL and implemented on an Altera FLEX10 FPGA. The main features of the proposed architecture are: (1) no explicit downsampling block is used, and downsampling is effected using a multiclock scheme, rather than using a separate dedicated block for the decimation function; multiplierless implementation through the exclusive use of biorthogonal B-spline filters; Modular architecture that allows extension to an arbitrary number of decomposition levels by simply cascading a basic module. Simulation results show that the proposed coding and decoding scheme is capable of producing high quality reconstructed signals.