FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability
Dong-Wook Lee, Manhwee Jo, Kyuseung Han, Ki‐Young Choi · 2009
This paper demonstrates a chip implementation of coarse-grained reconfigurable architecture named FloRA. Two-dimensional array of integer processing elements in the FloRA is configured in run-time to perform integer functions as well as floating-point functions. FloRA is implemented in Dongbu HiTek 130 nm process and evaluate by running applications including physics engine and JPEG decoder.