Reduced stall MIPS architecture using pre-fetching accelerator
Muhammad Zulkifli, Yusuf Purna Yudhanto, N.A. Soetharyo, Trio Adiono · 2009
This paper describes the design of a MIPS architecture with a small number of stall. Stall frequently happens in pipeline architecture which results in larger clock cycles. In this paper we significantly reduced stall by introducing pre-fetching unit. This unit reduces stall by concurrently reading three instructions and check their possibility of stall. If stall is detected, this unit then changes the sequence of executed instructions. Furthermore, we also employ forwarding and memory hazard detection units to further reduce stall. In order to increase the processor functionality and performances, especially for RSA security application, we include two new instructions 32-bit mult and mod. The design has been successfully implemented in FPGA DE2 Board (Terasic) and standard call CMOS 0.13u. As system verification, we successfully execute bubble sort program and RSA encryption. The system implementation reach the maximum frequency of 714 MHz.