Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters · 2007
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach.