Design and implementation of area-optimized AES based on FPGA
Aiwen Luo, Qingming Yi, Min Shi · 2011
A new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed in this paper. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 128-bit plaintext and the 128-bit initial key, as well as the 128-bit output of ciphertext, are all divided into four 32-bit consecutive units respectively controlled by the clock. The synthesis verification based on HJTC0.18um CMOS process shows that this new program can significantly decrease quantity of chip pins and effectively optimize the area of chip.