A 5.6 MIPS call-handling processor for switching systems
T. Hayashi, Yasuaki Saita, Toshiaki Ohno, T. Morita, T. Fukuda, Shinji Yoshida, R. Ikeda · IEEE Journal of Solid-State Circuits · 1989
A 32 bit call-handling processor for an electronic switching system (ESS) capable of a 5.6 MIPS instruction execution rate is discussed. The processor uses a mixed architecture consisting of a reduced instruction set computer (RISC) and a complex instruction set computer (CISC) to economize the instruction execution, and features a four-stage two-way pipeline and local storage for the RISC and writable control storage for the CISC. To obtain reliability, availability, and serviceability, such functions as parity check/generation, microdiagnostic, and matcher have been incorporated within the chip. The chip contains about 160 K transistors within a chip size of 13.2*13.7 mm/sup 2/. A 1.2 mu m double-metal CMOS technology has been used. In designing the chip layout, a compromise between manual and automatic placing or routing was adopted which enabled a reasonably short design time.>