Spyder: a reconfigurable VLIW processor using FPGAs
Christian Iseli, Eduardo García Sánchez · 2002
A processor with multiple reconfigurable execution units has been designed and implemented. The reconfigurable execution units are implemented using reprogrammable field programmable gate array (FPGA) chips. The architecture and implementation of this processor are described in detail. An example shows that this reconfigurable processor is able to compute the new state of 100'000'000 cells of Conway's game of life per second with a clock speed of 6.25 MHz.>